/*--------------------------------------------------------------------------
REG52.H

Header file for generic 80C52 and 80C32 microcontroller.
Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc.
All rights reserved.
--------------------------------------------------------------------------*/

#ifndef __REG52_H__
#define __REG52_H__

/*  BYTE Registers  */		  
sfr P0    = 0x80;
sfr P1    = 0x90;
sfr P2    = 0xA0;
sfr P3    = 0xB0;
sfr PSW   = 0xD0;
sfr ACC   = 0xE0;
sfr B     = 0xF0;
sfr SP    = 0x81;
sfr DPL   = 0x82;
sfr DPH   = 0x83;
sfr PCON  = 0x87;
sfr TCON  = 0x88;
sfr TMOD  = 0x89;
sfr TL0   = 0x8A;
sfr TL1   = 0x8B;
sfr TH0   = 0x8C;
sfr TH1   = 0x8D;
sfr IE    = 0xA8;
sfr IP    = 0xB8;
//sfr SCON  = 0x98;
//sfr SBUF  = 0x99;

/*  8052 Extensions  */
sfr T2CON  = 0xC8;
sfr RCAP2L = 0xCA;
sfr RCAP2H = 0xCB;
sfr TL2    = 0xCC;
sfr TH2    = 0xCD;

/*  M8051W Extensions  */
sfr	IP1	   = 0xF8;
sfr	IE1    = 0xE8;
sfr	IPH1   = 0xF9;
sfr IPH    = 0xB9;
sfr EO	   = 0xA2;

/* peripherals Extensions */
/*  UART  */
sfr UART_RXB = 	0x84;
sfr UART_THR =	0x84;
sfr UART_IER =	0x85;
sfr UART_IIR =	0x86;
sfr UART_FCR =	0x86;
sfr UART_LCR =  0x98;
sfr UART_LSR =	0x99;
sfr UART_TL  =	0xA1;

/* SPI  */
sfr SPI_PRER = 0x8E;
sfr SPI_CR   = 0x8F;
sfr SPI_SR   = 0x91;
sfr SPI_RXR  = 0x92;
sfr SPI_TXR  = 0x92;

sfr SPI2_PRER = 0x93;
sfr SPI2_CR   = 0x94;
sfr SPI2_SR   = 0x95;
sfr SPI2_RXR  = 0x96;
sfr SPI2_TXR  = 0x96;

/* I2C */
sfr I2C_PRERLO = 0x9A;
sfr I2C_PRERHI = 0x9B;
sfr I2C_CTR    = 0x9C;
sfr I2C_TXR	   = 0x9D;
sfr I2C_RXR    = 0x9D;
sfr I2C_CR     = 0x9E;
sfr	I2C_SR     = 0x9E;

/* PWM */
sfr PWM_CLK_CON = 0xA3;
sfr PWM_CNT_CON = 0xA4;
sfr PWM_CP_CON_0 = 0xA5;
sfr PWM_CP_CON_1 = 0xA6;
sfr PWM_CP_CON_2 = 0xA7;
sfr PWM_CP_CON_3 = 0xAA;
sfr PWM_COUNT_H  = 0xAB;
sfr PWM_COUNT_L  = 0xAC;
sfr PWM_COMP0_H  = 0xAD;
sfr PWM_COMP0_L  = 0xAE;
sfr PWM_COMP1_H  = 0xAF;
sfr PWM_COMP1_L  = 0xBA;
sfr PWM_COMP2_H  = 0xBB;
sfr PWM_COMP2_L	 = 0xBC;
sfr PWM_COMP3_H  = 0xBD;
sfr PWM_COMP3_L  = 0xBE;
sfr PWM_IF		 = 0xBF;

/*  CAN   */
/* COMMAN */
sfr CAN_BUSTIMING0 = 0xDF;
sfr CAN_BUSTIMING1 = 0xE1;
sfr CAN_CLOCK_DIVIDER = 0xFA;


/*  BASIC_CAN  */
sfr CAN_BASIC_CONTROL = 0XD9 ;
sfr CAN_BASIC_COMMAND = 0xDA  ;
sfr CAN_BASIC_STATUS  = 0xDB   ;
sfr	CAN_BASIC_INTERRUPT = 0xDC	;
sfr CAN_BASIC_ACCEP_CODE = 0xDD	 ;
sfr CAN_BASIC_ACCEP_MASK = 0xDE	  ;
								   
sfr CAN_TRANS_ID1 		= 0xE2		;
sfr CAN_TRANS_ID2		= 0xE3		;
sfr CAN_TRANS_DATA1		= 0xE4		;
sfr CAN_TRANS_DATA2		= 0xE5		;
sfr CAN_TRANS_DATA3		= 0xE6		;
sfr CAN_TRANS_DATA4		= 0xE7		;
sfr CAN_TRANS_DATA5     = 0xE9		;
sfr CAN_TRANS_DATA6		= 0xEA		;
sfr CAN_TRANS_DATA7		= 0xEB		;
sfr CAN_TRANS_DATA8 	= 0xEC		;

sfr CAN_RECEIVE_ID1 	= 0xED		;
sfr CAN_RECEIVE_ID2		= 0xEE		;
sfr CAN_RECEIVE_DATA1	= 0xEF		;
sfr CAN_RECEIVE_DATA2	= 0xF1		;
sfr CAN_RECEIVE_DATA3	= 0xF2		;
sfr CAN_RECEIVE_DATA4	= 0xF3		;
sfr CAN_RECEIVE_DATA5   = 0xF4		;
sfr CAN_RECEIVE_DATA6	= 0xF5		;
sfr CAN_RECEIVE_DATA7	= 0xF6		;
sfr CAN_RECEIVE_DATA8 	= 0xF7		;
									
/* PeliCan */
sfr	CAN_PELI_MOD		= 0xD9		;
sfr	CAN_PELI_COMMAND	= 0xDA;	
sfr CAN_PELI_STATUS		= 0xDB;
sfr CAN_PELI_INTERRUPT	= 0xDC;
sfr CAN_PELI_IE			= 0xDD;
sfr	CAN_PELI_ARBITRATION_LOST = 0xE3;
sfr	CAN_PELI_ERROR_CODE = 0xE4;
sfr	CAN_PELI_ERROR_WARNNING_LIMMIT = 0xE5;
sfr	CAN_PELI_RX_ERROR_CNT = 0xE6;
sfr	CAN_PELI_TX_ERROR_CNT = 0xE7;
sfr	CAN_PELI_BUFFER_0		= 0xE9;
sfr	CAN_PELI_BUFFER_1		= 0xEA;
sfr CAN_PELI_BUFFER_2		= 0xEB;
sfr	CAN_PELI_BUFFER_3		= 0xEC;
sfr	CAN_PELI_BUFFER_4		= 0xED;
sfr	CAN_PELI_BUFFER_5		= 0xEE;
sfr	CAN_PELI_BUFFER_6		= 0xEF;
sfr	CAN_PELI_BUFFER_7		= 0xF1;
sfr	CAN_PELI_BUFFER_8		= 0xF2;
sfr	CAN_PELI_BUFFER_9		= 0xF3;
sfr	CAN_PELI_BUFFER_10		= 0xF4;
sfr	CAN_PELI_BUFFER_11		= 0xF5;
sfr	CAN_PELI_BUFFER_12		= 0xF6;
sfr	CAN_PELI_ACCPTANCE_CODE_0 = 0xE9;
sfr	CAN_PELI_ACCPTANCE_CODE_1 = 0xEA;
sfr	CAN_PELI_ACCPTANCE_CODE_2 = 0xEB;
sfr	CAN_PELI_ACCPTANCE_CODE_3 = 0xEC;
sfr	CAN_PELI_ACCPTANCE_MASK_0 = 0xED;
sfr	CAN_PELI_ACCPTANCE_MASK_1 = 0xEE;
sfr	CAN_PELI_ACCPTANCE_MASK_2 = 0xEF;
sfr	CAN_PELI_ACCPTANCE_MASK_3 = 0xF1;
sfr	CAN_PELI_RX_MESSAGE_CNT	  = 0xF7;

/*  BIT Registers  */
/*  PSW  */
sbit CY    = PSW^7;
sbit AC    = PSW^6;
sbit F0    = PSW^5;
sbit RS1   = PSW^4;
sbit RS0   = PSW^3;
sbit OV    = PSW^2;
sbit P     = PSW^0; //8052 only

/*  TCON  */
sbit TF1   = TCON^7;
sbit TR1   = TCON^6;
sbit TF0   = TCON^5;
sbit TR0   = TCON^4;
sbit TIE1   = TCON^3;
sbit IT1   = TCON^2;
sbit IE0   = TCON^1;
sbit IT0   = TCON^0;

/*  IE  */
sbit EA    = IE^7;
sbit ET2   = IE^5; //8052 only
sbit ES    = IE^4;
sbit ET1   = IE^3;
sbit EX1   = IE^2;
sbit ET0   = IE^1;
sbit EX0   = IE^0;

sbit EUART = IE^4;
sbit ESPI  = IE1^0;
sbit ESPI2 = IE1^1;
sbit ECAN  = IE1^2;
sbit ECAN2 = IE1^3;
sbit EI2C  = IE1^4;
sbit EPWM  = IE1^5;


/*  IP  */
sbit PT2   = IP^5;
sbit PS    = IP^4;
sbit PT1   = IP^3;
sbit PX1   = IP^2;
sbit PT0   = IP^1;
sbit PX0   = IP^0;

/*  P3  */
sbit RD    = P3^7;
sbit WR    = P3^6;
sbit T1    = P3^5;
sbit T0    = P3^4;
sbit INT1  = P3^3;
sbit INT0  = P3^2;
sbit TXD   = P3^1;
sbit RXD   = P3^0;

/*  SCON  */
//sbit SM0   = SCON^7;
//sbit SM1   = SCON^6;
//sbit SM2   = SCON^5;
//sbit REN   = SCON^4;
//sbit TB8   = SCON^3;
//sbit RB8   = SCON^2;
//sbit TI    = SCON^1;
//sbit RI    = SCON^0;

/*  P1  */
sbit T2EX  = P1^1; // 8052 only
sbit T2    = P1^0; // 8052 only
             
/*  T2CON  */
sbit TF2    = T2CON^7;
sbit EXF2   = T2CON^6;
sbit RCLK   = T2CON^5;
sbit TCLK   = T2CON^4;
sbit EXEN2  = T2CON^3;
sbit TR2    = T2CON^2;
sbit C_T2   = T2CON^1;
sbit CP_RL2 = T2CON^0;

#endif
